However, when the charge and discharge of the gate of the power element are performed, there exists a dead time that the start timing of operation of the power element is delayed to the rising timing or the falling timing of the control signal, due to the charge time and discharge time required for the gate voltage of the power element to exceed a threshold voltage. In order to shorten this dead time, it is necessary to shorten the time required for the gate voltage to reach the threshold. However, according to the technology described in Patent Literature 1, it is necessary to optimize the detection voltage that detects the gate voltage, matching well with the threshold voltage for every power element. Therefore, according to the technology described in Patent Literature 1, it is necessary to obtain matching between the threshold voltage of the power element and the circuit operation of the gate driver; however, it is difficult to perform the optimal operation of the gate driver for the power element used.
The other issues and new features of the present invention will become clear from the description of the present specification and the accompanying drawings.
According to one embodiment, a semiconductor device monitors a collector voltage of a power element when turning off the power element, and increases the number of NMOS transistors that draw out charges from a gate of the power element in a period until the collector voltage becomes lower than a determination threshold set in advance, rather than after the collector voltage becomes lower than the determination threshold.
According to the one embodiment, it is possible to provide a gate driver that performs the optimal operation for the power element, irrespective of the threshold voltage of the power element.